Analog video chromakey mixer

ABSTRACT

An improved technique for mixing picture signals directed at a monitor screen. Two analog video signals (such as an analog VGA input and an analog RGB signal produced in response to a stored digital still or moving image) may be multiplexed in analog form. An analog chromakey mixer detects a background color in the first video signal (such as the analog VGA input), and replaces the portion of that first video signal with the second video signal. The time delays of the first video and the second video signal may be adjusted so that they reach the monitor screen (by means o a multiplexer output) at the same time. An alignment detector may attempt to align chromakey mixer until the time difference between the first and the second video signals falls below a threshold.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an analog video chromakey mixer.

2. Description of Related Art

When still or moving images in digital form are displayed in a computersystem, the digital images must generally be decoded and displayed asimages on a computer monitor screen. Typically, the monitor screen isthe only monitor screen in the computer system. However, those decodedand displayed images must be coordinated with other display signalsdirected at the same monitor screen, such as those signals directed thatthe monitor screen by an RGB or VGA monitor driver. Typically, the twosets of signals directed at the monitor screen must be multiplexed insome way.

Generally, it is desired that the two sets of signals must be smoothlymultiplexed, with no breaks that would be visible to the human eye. Itis also generally desired that the two sets of signals should bemultiplexed quickly, so that high quality, high speed images may bedisplayed. It is also generally desired that any method for multiplexingthe two sets of signals should work with a wide variety of computersystems and with a minimum of adaptation required for any of them.

However, one problem that has arisen in the art is that high quality,high speed multiplexing of analog and digital video signals can bedifficult. For example, if it were desired to digitize the analog videosignals and multiplex them with the digital signals entirely digitally,it could require an A/D converter that produced 16 million colors (24bits) at a 75 MHz pixel rate. Present A/D converters do not operate atthis combination of precision and speed, at least not at anything near areasonable cost for a personal computer system.

One method of the prior art has been to multiplex the digital dataprovided by the computer system's processor (or CPU) to the monitordriver. While this method sometimes achieves the goal of synchronizingdigital and analog video sources, it has the drawback that it requiressubstantial information about the method of color encoding used by theVGA monitor driver. As monitor drivers have been changed withimprovements in monitors and in drivers, this method also has thedrawback that it may fail to work for certain classes of monitordrivers.

Accordingly, it is an object of the invention to provide an improvedtechnique for mixing picture signals directed at a monitor screen.

SUMMARY OF THE INVENTION

The invention provides an improved technique for mixing picture signalsdirected at a monitor screen.

In a preferred embodiment, two analog video signals, such as an analogVGA input and an analog RGB signal produced in response to a storeddigital still or moving image, may be multiplexed in analog form. Ananalog chromakey mixer detects a background color in the first videosignal and replaces the portion of that first video signal with thesecond video signal.

In a preferred embodiment, the time delays of the first video signal andthe second video signal may be adjusted so that they reach the monitorscreen (by means of a multiplexer output) at the same time. An alignmentdetector may attempt to align two known signals (such as a VGA syncsignal and a signal generated for this purpose), and may adjust a set oftime delays in the analog chromakey mixer until the time differencebetween the first and second video signals falls below a threshold.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a video system architecture.

FIG. 2 shows a block diagram of an analog chromakey mixer.

FIG. 3 shows signal waveforms for video signal matching.

DESCRIPTION OF THE PREFERRED EMBODIMENT System Architecture

FIG. 1 shows a video system architecture.

In a preferred embodiment, a video system 101 embedded in a computersystem comprises a VGA input 102, having a sync input 103 for ahorizontal sync (HS) signal 104 and a vertical sync (VS) signal 105, andhaving a first video input 106 for a first analog signal 107 (such as ananalog RGB video signal). In a preferred embodiment, the VGA input 102may be coupled to a VGA monitor driver, such as a personal computersystem comprising a monitor driver card or another monitor drivercircuit. VGA monitor drivers are known in the art. The sync input 103 iscoupled to a sync output 108.

The sync input 103 and the first analog signal 107 are coupled to ananalog chromakey mixer 109, which detects a key color in the analog RGBvideo signal and multiplexes the first analog signal 107 with a secondanalog RGB signal.

The analog chromakey mixer 109 is coupled to a set of reference voltages110, comprising a +5 volt source and a −5 volt source in a preferredembodiment, to a CCLK signal 111 and a CDATA signal 112, forcommunication with the computer system, to a PCLK signal 113 and a VRDYsignal 114, and to a second video input 115. The analog chromakey mixer109 provides an output FBLANK signal 116 and an output FCLOCK signal117, and a video output 118.

The sync input 103 is coupled to a digital signal processor (DSP) 119,which provides a digital video signal 120 having a sequence of digitalpixels. The DSP 119 is coupled to the FBLANK signal 116 and the FCLOCKsignal 117 from the analog chromakey mixer 109. The DSP 119 provides thePCLK signal 113 and the VRDY signal 114.

The digital video signal 120 is coupled to a video D/A converter 121,which converts the digital video signal 120 to a second analog signal122 having a sequence of analog pixels. The second analog signal 122 iscoupled to the analog chromakey mixer 109 at the second video input 115.

System Operation

In a preferred embodiment, the HS signal 104 and the VS signal 105provide sync information for the first analog signal 107, and for themultiplexed video signal coupled to the video output 118.

The analog chromakey mixer 109 is described in further detail withreference to FIG. 2.

The reference voltages 110 provide power and logical references for theanalog chromakey mixer 109. Reference voltages are known in the art. Ina preferred embodiment, the reference voltages 110 may also be coupledto other circuits for similar purposes.

The CCLK signal 111 and a CDATA signal 112 are for communication withthe computer system. These signals are used by the computer system toprogram voltage reference levels and internal registers of the analogchromakey mixer chip 109. Programming reference levels and internalregisters of a chip by means of input signals is known in the art.

The PCLK signal 113 is a clock for the VRDY signal 114. The VRDY signal114 indicates whether a digital pixel in the a digital video signal 120comprises valid data.

The FBLANK signal 116 provides a composite blanking signal for the DSP119. The FCLOCK signal 117 provides a pixel clock for the DSP 119.

In a preferred embodiment, the DSP 119 may comprise the Piccolo chip(available from Sigma Designs, Inc., of Fremont, Calif.).

In a preferred embodiment, the digital video signal 120 comprises asequence of digital pixels, each having 8 bits of precision for each ofthree colors (red, green, and blue), at a rate of about 20 nanosecondsper digital pixel.

The D/A converter 121 converts each digital pixel to a set of threeanalog voltages, one for each of three colors. D/A converters are knownin the art. In a preferred embodiment, the D/A converter 121 maycomprise the BT121 device (available from Brooktree Corporation of SanDiego, Calif.).

Analog Chromakey Mixer

FIG. 2 shows a block diagram of an analog chromakey mixer.

In a preferred embodiment, the HS signal 104 is coupled to a line lockedphase locked loop (PLL) 201, which recovers a clock signal from the HSsignal 104. Phase locked loops are known in the art. The line locked PLL201 is coupled to a phase adjuster 202, which provides an adjustabledelay. An output of the phase adjuster 202 provides the FCLOCK signal117. The phase adjuster 202 is coupled to a counter 203, which providesthe FBLANK signal 116.

The HS signal 104 and the VS signal 105 are coupled to a polaritydetector 204. In a preferred embodiment, the HS signal 104 and the VSsignal 105 may have any polarity. The polarity detector 201 uses theFCLOCK signal 117 to sample the HS signal 104; if the same value issampled for more than 256 consecutive clock pulses, that value isconsidered to represent the inverse of the polarity of the HS signal104. Similarly, the polarity detector 201 uses the FCLOCK signal 117 tosample the VS signal 105; if the same value is sampled for more than 256consecutive clock pulses, that value is considered to represent theinverse of the polarity of the VS signal 105.

The first analog signal 107 is coupled to a chromakey detector 205,which determines whether a present analog pixel of the analog RGB videosignal matches the color to be replaced (the chromakey). The chromakeydetector 205 is coupled to a set of six D/A converters 206 that providea set of three minimum/maximum values for the red (R), green (G), andblue (B) color components of the analog RGB video signal. The chromakeydetector 205 determines a color match when the detected color fallswithin the minimum/maximum values for all three color components, andgenerates a match signal 208.

The first analog signal 107 is coupled, by means of a delay 207, to afirst input of an analog multiplexer 209.

The CCLK signal 111 and the CDATA signal 112 are coupled to a controlcircuit 210, for programming voltage reference levels and internalregisters of the analog chromakey mixer chip 109. Programming referencelevels and internal registers of a chip by means of input signals isknown in the art.

The PCLK signal 113 is used to clock the VRDY signal 114 to an input ofa programmable delay 211, which provides an output VRDY1 signal 212. TheVRDY1 signal 212 is coupled to a fine delay 213, which provides anoutput VRDY2 signal 214. The VRDY2 signal is coupled to an input of alogical AND gate 215.

The match signal 208 is coupled to another input of the logical AND gate215. An output of the logical AND gate 215 is coupled to a select inputof the analog multiplexer 209. The second analog signal 122 is coupledto a second input of the analog multiplexer 209. An output of the analogmultiplexer 209 is coupled to the video output 118.

Analog Chromakey Mixer Operation

In a preferred embodiment, the chromakey detector 205 detects thechromakey in the first analog signal 107; the match signal 208 indicatesthat the chromakey detector 205 found a match. When a match is found, atthe next valid pixel from the D/A converter 121, the match signal 208and the VRDY signal 114 will both be logical “1”, and the logical ANDgate 215 will cause the analog multiplexer 209 to select the secondanalog signal 122 instead of the first analog signal 107.

A cumulative time delay t1 between input and output of the first analogsignal 107 may comprise time delays as shown in table 2-1:

TABLE 2-1 Time Delay Cause of Time Delay t251 from the first video input106 to an input of the delay 207 t252 across the delay 207 t253 from theoutput of the delay 207 to the output of the analog multiplexer 209Thus, t1 = t251 + t252 + t253, where t252 is adjustable.

A cumulative time delay t2 between input and output of the second videosignal 122 may comprise time delays as shown in table 2-2:

TABLE 2-2 Time Delay Cause of Time Delay t261 across the line locked PLL201 t262 across the phase adjuster 202 t263 from the output of theFCLOCK signal 117 to the output of the digital video signal 120 from theDSP 119 t264 across the D/A converter 121 t265 from the output of theD/A converter 121 to the output of the analog multiplexer 209 Thus, t2 =t261 + t262 + t263 + t264 + t265, where t262 is adjustable.

A cumulative time delay t3 between input and output of the first videosignal 107 may alternatively comprise time delays as shown in table 2-3:

TABLE 2-3 Time Delay Cause of Time Delay t251 from the first video input106 to an input of the delay 207 t272 from the input of the delay 207 tothe output of the chroma- key detector 205 t273 from the output of thechromakey detector 205 to the output of the logical AND gate 215 t274from the output of the logical AND gate 215 to the output of the analogmultiplexer 209 Thus, t3 = t251 + t272 + t273 + t274, where none ofthese values is adjustable.

A cumulative time delay t4 between input and output of the second videosignal 122 may alternatively comprise time delays as shown in table 2-4:

TABLE 2-4 Time Delay Cause of Time Delay t261 across the line locked PLL201 t262 across the phase adjuster 202 t283 from the output of theFCLOCK signal 117 to the output of the VRDY signal 114 from the DSP 119t284 across the programmable delay 211 t285 across the fine delay 213t286 from the output of the fine delay 213 to the output of the logicalAND gate 215 t274 from the output of the logical AND gate 215 to theoutput of the analog multiplexer 209 Thus, t4 = t261 + t262 + t283 +t284 + t285 + t286 + t274, where t262, t284, and t285 are adjustable.

In a preferred embodiment, all four cumulative time delays must beequal: t1=t2=t3=t4. Each time delay t1, t2, and t4, comprises at leastone adjustable time delay. Cumulative time delay t1 comprises adjustabletime delay t252. Cumulative time delay t2 comprises adjustable timedelay t262. Cumulative time delay t4 comprises adjustable time delayst262, t284, and t285. Accordingly, adjusting time delays t252, t262,t284, and t285, allows all four cumulative time delays t1, t2, t3, andt4, to be adjusted until they are equal.

An alignment detector 216 is coupled to an output of the analogmultiplexer 209. The alignment detector 216 is also coupled to a set ofcontrol lines 217, coupled to each device that controls an adjustabletime delay: delay 207 (controlling time delay t252), phase adjuster 202(controlling time delay t262), programmable delay 211 (controlling timedelay t284), and fine delay 213 (controlling time delay t285).

In a preferred embodiment, delay 207 and programmable delay 211 may beset when the analog chromakey mixer 109 is manufactured, so that t1=t3.Thus, only t2 and t4 need to be adjusted, by adjusting t262 and t285.

Video Signal Matching

FIG. 3 shows signal waveforms for video signal matching.

In a preferred embodiment, the alignment detector 216 may operate whenthe video system 101 is first powered on, or when the video system 101is reset. During operation of the alignment detector 216, a first testsignal 301 is generated and coupled to the first signal input 106 of thevideo system 101. The first test signal 301 comprises a sequence ofspikes 302 of a first color, with a black background. A second testsignal 303 is generated by the DSP 119 and coupled to the video system101 as the digital video signal 120. The second test signal 303comprises a background of a second color, with a sequence of blackspikes 304.

The chromakey is set so that the positive voltage spikes 302 of thefirst test signal 301 are replaced by the black spikes 304 of the secondtest signal 303. The first test signal 301 and the second test signal303 are generated so that when properly aligned, the output signal 305from the video output 118 will be completely black.

The alignment detector 216 detects any color spikes in the output signal305, whether the first color or the second color. If color spikes arenot present, the first test signal 301 and the second test signal 303are perfectly aligned, and no adjustment of time delays is needed. Ifcolor spikes are present, the first test signal 301 and the second testsignal 303 are not perfectly aligned, and one or more time delays mustbe adjusted to obtain perfect alignment.

The alignment detector 216 adjusts the values of the time delays t262and t285 until there are no color spikes (or at least until the colorspikes are minimized) in the output signal 305. In a preferredembodiment, there are about 64 possible values for time delay t262 andabout 64 possible values for time delay t285, so it is possible for thealignment detector 216 to try all possible values of time delays t262and t285 in only a few seconds. Thereafter, there is no need to adjustany of the time delays further.

Alternative Embodiments

While preferred embodiments are disclosed herein, many variations arepossible which remain within the concept and scope of the invention, andthese variations would become clear to one of ordinary skill in the artafter perusal of the specification, drawings and claims herein.

I claim:
 1. A device, comprising means for receiving a first analogvideo signal; means for receiving a second analog video signal; meansfor detecting a chromakey in said first analog video signal and forgenerating a comparison signal in response thereto; means for replacinga portion of said first analog video signal with a portion of saidsecond analog video signal in response to said comparison signal; meansfor measuring a difference between a first time delay and a second timedelay, said first time delay comprising a delay from input to output ofsaid first analog video signal, said second time delay comprising adelay from input to output of said second analog video signal; and meansfor adjusting said at least one time delay, so that said first timedelay and said second time delay are substantially equal.
 2. A device asin claim 1, wherein said means for adjusting comprises means forsupplying a selected first video input to said means for receiving saidfirst analog video signal; means for supplying a selected second videoinput to said means for receiving said second analog video signal; meansfor comparing an output of said means for replacing with a selectedanalog video signal; and means for controlling at least one time delaycircuit in response to said means for comparing.
 3. A device as in claim1, wherein said means for adjusting comprises means for supplying aselected first video input to said means for receiving said first analogvideo signal; means for supplying a selected second video input to saidmeans for receiving said second analog video signal; means for comparingan output of said means for replacing with a selected analog videosignal; and means for controlling at least one time delay circuit tominimize a difference between said output of said means for replacingand said selected analog video signal.
 4. A device as in claim 1,wherein said means for adjusting comprises means for supplying aselected first video input to said means for receiving said first analogvideo signal; means for supplying a selected second video input to saidmeans for receiving said second analog video signal; means for comparingan output of said means for replacing with a selected analog videosignal; means for tentatively selecting a first and a second one of aplurality of possible time delays for said time delay circuit; means forexamining an output of said means for comparing for said first and saidsecond one possible time delays, responsive to said means fortentatively selecting; and means for permanently selecting said first orsaid second one possible time delay in response to said means forexamining.
 5. A device as in claim 4, wherein said means for tentativelyselecting repeatedly selects possible combinations of time delays for aplurality of time delay circuits until a difference between said outputof said means for replacing and said selected analog video signal fallsbelow a selected threshold.
 6. A device as in claim 4, wherein saidmeans for tentatively selecting selects substantially all possiblecombinations of time delays for a plurality of time delay circuits, andwherein said means for permanently selecting selects one of saidsubstantially all possible combinations that minimizes a differencebetween said output of said means for replacing and said selected analogvideo signal.
 7. A device as in claim 1, wherein said first analog videosignal is an analog VGA input.
 8. A device as in claim 1, wherein saidmeans for replacing comprises an analog multiplexer coupled to saidfirst analog video signal, said second analog video signal, and saidcomparison signal.
 9. A device as in claim 1, wherein said second analogvideo signal is an analog RGB signal produced in response to a storeddigital still or moving image.
 10. A method comprising the steps ofreceiving a first analog video signal; receiving a second analog videosignal; detecting a chromakey in said first analog video signal andgenerating a comparison signal in response thereto; replacing a portionof said first analog video signal with a portion of said second analogvideo signal in response to said comparison signal; adjusting at leastone time delay between said means for receiving a first analog videosignal and said means for replacing; measuring a difference between afirst time delay and a second time delay, said first time delaycomprising a delay from input to output of said first analog videosignal, said second time delay comprising a delay from input to outputof said second analog video signal; and adjusting at least one timedelay, so that said first time delay and said second time delay aresubstantially equal.
 11. A method as in claim 10, wherein said step ofadjusting comprises the steps of supplying a selected first video input;supplying a selected second video input; comparing a result of said stepof replacing with a selected analog video signal; and controlling atleast one time delay circuit in response to said step of comparing. 12.A method as in claim 10, wherein said step of adjusting comprises thesteps of supplying a selected first video input; supplying a selectedsecond video input; comparing a result of said step of replacing with aselected analog video signal; and controlling at least one time delaycircuit to minimize a difference between said result of said step ofreplacing and said selected analog video signal.
 13. A method as inclaim 10, wherein said step of adjusting comprises the steps ofsupplying a selected first video input; supplying a selected secondvideo input; comparing a result of said step of replacing with aselected analog video signal; tentatively selecting a first and a secondone of a plurality of possible time delays for said time delay;examining a result of said step of comparing for said first and saidsecond one possible time delays; and permanently selecting said first orsaid second one possible time delay in response to said step ofexamining.
 14. A method as in claim 13, wherein said step of tentativelyselecting selects substantially all possible combinations of time delaysfor a plurality of time delay circuits, and wherein said step ofpermanently selecting selects one of said substantially all possiblecombinations that minimizes a difference between said result of saidstep of replacing and said selected analog video signal.
 15. A method asin claim 13, wherein said step of tentatively selecting is performedrepeatedly to select possible combinations of time delays for aplurality of time delay circuits until a difference between said resultof said step of replacing and said selected analog video signal fallsbelow a selected threshold.
 16. A method as in claim 14, wherein saidstep of receiving a second analog video signal comprises the steps ofproducing an analog RGB signal in response to a stored digital still ormoving image, and receiving said analog RGB signal.
 17. A method as inclaim 14, wherein said step of replacing comprises the step of using ananalog multiplexer coupled to said first analog video signal, saidsecond analog video signal, and said comparison signal.
 18. A methodcomprising the steps of: receiving a first analog video signal;converting a source of digital video to a second analog video signal;mixing said first analog video signal and said second analog videosignal; measuring a difference between a first time delay and a secondtime delay, said first time delay comprising a delay from input tooutput of said first analog video signal, said second time delaycomprising a delay from input to output of said second analog videosignal; and adjusting at least one time delay, so that said first timedelay and said second time delay are substantially equal.
 19. A videosystem as in claim 18, comprising the step of displaying a result ofsaid step of multiplexing.
 20. A method comprising the steps of:receiving a first analog video signal; detecting a chromakey in saidfirst analog video signal; converting a source of digital video to asecond analog video signal; replacing a portion of said first analogvideo signal with a portion of said second analog video signal inresponse to said chromakey; measuring a difference between a first timedelay and a second time delay, said first time delay comprising a delayfrom input to output of said first analog video signal, said second timedelay comprising a delay from input to output of said second analogvideo signal; and adjusting at least one time delay, so that said firsttime delay and said second time delay are substantially equal.
 21. Amethod as in claim 20, comprising the step of displaying a result ofsaid step of replacing.
 22. A device as in claim 2, wherein saidselected analog video signal comprises an all-black signal.
 23. A methodas in claim 11, wherein said selected analog video signal comprises anall-black signal.
 24. Apparatus including a first input port disposedfor receiving a first analog video signal; a second input port disposedfor receiving a second analog video signal; a chromakey detector coupledto said first input port; a multiplexer coupled to said chromakeydetector, said first input port, and said second input port; an outputport coupled to said multiplexer; an adjusting circuit disposed foradjusting a time delay in said apparatus, whereby a difference isminimized between a first time delay between said first input port andsaid output port and a second time delay between said second input portand said output port.
 25. Apparatus as in claim 24, including a clockinput port disposed for receiving a clock signal; and a detector coupledto said output port, said detector being responsive to an output signalappearing at said output port, said output signal including a pluralityof horizontal lines each having a plurality of pixels, said pixels beingresponsive to said clock signal.
 26. Apparatus as in claim 24, includinga control input port disposed for receiving a signal indicative of astatus of said second analog video signal.
 27. Apparatus as in claim 26,including a circuit coupled to said control input port, to saidchromakey detector, and to said multiplexer.
 28. Apparatus as in claim24, including a detector coupled to said output port, said detectorbeing responsive to an output signal appearing at said output port, saidoutput signal including a plurality of horizontal lines each having aplurality of pixels.
 29. Apparatus as in claim 24, wherein said timedelay includes a time delay between said chromakey detector and saidmultiplexer.
 30. Apparatus as in claim 24, wherein said time delayincludes a time delay between said first input port and said chromakeydetector.
 31. Apparatus as in claim 24, wherein said time delay includesa time delay between said first input port and said multiplexer. 32.Apparatus as in claim 24, wherein said time delay includes a time delaybetween said second input port and said chromakey detector. 33.Apparatus as in claim 24, wherein said time delay includes a time delaybetween said second input port and said multiplexer.
 34. Apparatus as inclaim 24, wherein said time delay includes a coarse time delay and afine time delay.
 35. A method including the steps of receiving a firstanalog video signal; receiving a second analog video signal; detecting achromakey in said first analog video signal; replacing at least aportion of said analog video signal with at least a portion of saidsecond analog video signal in response to said chromakey; outputting aresultant signal of said step of replacing; adjusting a time delay,whereby a difference is minimized between a first time delay betweensaid step of receiving said first analog video signal and said step ofoutputting and a second time delay between said step of receiving saidsecond analog video signal and said step of outputting.
 36. A method asin claim 35, including the steps of receiving a clock signal; anddetecting said resultant signal, said resultant signal including aplurality of horizontal lines each having a plurality of pixels, saidpixels being responsive to said clock signal.
 37. A method as in claim35, including the step of receiving a control signal, said controlsignal being indicative of a status of said second analog video signal.38. A method as in claim 37, wherein said step of replacing isresponsive to said control signal.
 39. A method as in claim 35,including the step of detecting said resultant signal, wherein saidresultant signal includes a plurality of horizontal lines each having aplurality of pixels.
 40. A method as in claim 35, wherein said timedelay includes a time delay between said step of detecting a chromakeyand said step of replacing.
 41. A method as in claim 35, wherein saidtime delay includes a time delay between said step of receiving a firstanalog video signal and said step of detecting a chromakey.
 42. A methodas in claim 35, wherein said time delay includes a time delay betweensaid step of receiving a first analog video signal said step ofreplacing.
 43. A method as in claim 35, wherein said time delay includesa time delay between said step of receiving a second analog video signaland said step of detecting a chromakey.
 44. A method as in claim 35,wherein said time delay includes a time delay between said step ofreceiving a second analog video signal and said step of replacing.
 45. Amethod as in claim 35, wherein said time delay includes a coarse timedelay and a fine time delay.